The later release is probably also due to the higher degree of integration these products require, to design laptop chassis, system board and cooling around them, never mind the firmware optimizations. Manufacturing on leading edge nodes should also get more profitable for lower cost parts as time goes on - APUs have up until now been much cheaper than the desktop CPUs.
"AMD has also adjusted the L3 amount, to 4 MB per CCX, which is half that of the consumer desktop line."
That's not correct, it's only a quarter, since consumer desktop line now has 16 MB per CCX. (Raven Ridge had half that of the desktop line, IMHO it's slightly surprising that the cut this time is that drastic.)
Ian made an error in the article. That should say "8 MB per CCX" not "4 MB". And the lack of any I/O die (aka, the memory controller & uncore is all right on die) should make up for that reduction by reducing latency, just like using just 1x CCX did w/ Raven Ridge & Picasso.
Scratch that. It seems that dAMD DID actually cut the L3 by 3/4's (from 16MB to 4MB per CCX). That's really kinda surprising. Must mean that they got an even bigger latency benefit from bringing the IMC & uncore on die (from the desktop's separate 12nm I/O die) than I was originally expecting, such that the die space savings were more worth it than just cutting the L3 in 1/2 (aka doubling the L3 per CCX vs RR/Picassso), as was the case with prior APUs.
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extide - Monday, January 6, 2020 - link
Two CCX, it's right in the article.The Hardcard - Tuesday, January 7, 2020 - link
The charts and graphs pulled my eyes pass that short paragraph. I blame society.Spunjji - Tuesday, January 7, 2020 - link
We do, indeed, live in one of those. Or so I keep hearing.Hul8 - Tuesday, January 7, 2020 - link
The later release is probably also due to the higher degree of integration these products require, to design laptop chassis, system board and cooling around them, never mind the firmware optimizations. Manufacturing on leading edge nodes should also get more profitable for lower cost parts as time goes on - APUs have up until now been much cheaper than the desktop CPUs.mczak - Monday, January 6, 2020 - link
"AMD has also adjusted the L3 amount, to 4 MB per CCX, which is half that of the consumer desktop line."That's not correct, it's only a quarter, since consumer desktop line now has 16 MB per CCX.
(Raven Ridge had half that of the desktop line, IMHO it's slightly surprising that the cut this time is that drastic.)
brantron - Monday, January 6, 2020 - link
Between the integrated memory controller and "extra" L3 from unused CPU cores, they should come out closer to their desktop counterparts than before.AMD probably isn't too concerned with parity at 100% load. My laptop is a lowly dual-core, and I rarely, if ever, see that happen.
Cooe - Monday, January 6, 2020 - link
Ian made an error in the article. That should say "8 MB per CCX" not "4 MB". And the lack of any I/O die (aka, the memory controller & uncore is all right on die) should make up for that reduction by reducing latency, just like using just 1x CCX did w/ Raven Ridge & Picasso.Cooe - Monday, January 6, 2020 - link
Scratch that. It seems that dAMD DID actually cut the L3 by 3/4's (from 16MB to 4MB per CCX). That's really kinda surprising. Must mean that they got an even bigger latency benefit from bringing the IMC & uncore on die (from the desktop's separate 12nm I/O die) than I was originally expecting, such that the die space savings were more worth it than just cutting the L3 in 1/2 (aka doubling the L3 per CCX vs RR/Picassso), as was the case with prior APUs.Jugotta Bichokink - Tuesday, January 7, 2020 - link
Bigger cache is only shiny-useful in certain conditions, also needs watts. The sweet spot is calculated.nandnandnand - Monday, January 6, 2020 - link
Was a Ryzen 9 4900H even alluded to at the presentation? Or are other sites just mentioning it because it is the rumored top of the 45W stack?