New Technology Features for 2024: RibbonFETs

One of the major features of this roadmap is highlighted when it shifts to 20A, Intel’s process name referring to Angstroms rather than nanometers. At this juncture, as mentioned above, Intel will be transitioning from its FinFET design over to a new type of transistor, known as a Gate-All-Around transistor, or GAAFET. In Intel’s case, the marketing name they are giving their version is RibbonFET.

It has been widely expected that once the standard FinFET runs out of steam that the semiconductor manufacturing industry will pivot to GAAFET designs. Each of the leading edge vendors call their implementation something different (RibbonFET, MBCFET), but it is all using the same basic principle – a flexible width transistor with a number of layers helping drive transistor current. Where FinFETs relies on multiple quantized fins for source/drain and a cell height of multiple tracks of fins, GAAFETs enable a single fin of variable length, allowing the current for each individual cell device to be optimized in power, performance, or area.


Image from Samsung

Intel has been discussing GAAFETs in technical semiconductor conferences for a number of years, at the International VLSI conference in June 2020, then CTO Dr. Mike Mayberry showcased a diagram with the enhanced electrostatics of moving to a GAA design. At the time we asked about Intel’s timescale for implementing GAA in volume, and were told to expect them ‘within 5 years’. At present Intel’s RibbonFET is due to come with the 20A process, likely to be productized by the end of 2024 based on the roadmaps outlined above.

In Intel’s RibbonFET diagrams for this event, they’re showing both PMOS and NMOS devices, as well as what clearly looks like a 4-stack design. Given that I have seen presentations from Intel involving anything from 2-stack to 5-stack at the industry conferences, we confirmed that Intel will indeed be using a 4-stack implementation. The more stacks that are added, the more process node steps are required for manufacturing, and to quote Intel’s Dr. Kelleher, ‘it’s easier to remove a stack than to add one!’. Exactly what is the right number of stacks for any given process or function is still an active area of research, however Intel seems keen on four.

In comparison with Intel’s competitors,

TSMC is expected to transition to GAAFET designs on its 2nm process. At its annual Tech Symposium in August 2020, TSMC confirmed that it would remain on FinFET technology all the way to its 3nm (or N3) process node as it has been able to find significant updates to the technology to allow performance and leakage scaling beyond what was initially expected – N3 is quoted to have up to a 50% performance gain, 30% power reduction, or 1.7x density gain over TSMC N5. Staying on FinFETs, TSMC stated, provides comfort to its customers. Details on TSMC’s N2 have not been disclosed.

Samsung by contrast has stated that it will be introducing its GAA technology with its 3nm process node. Back in Q2 2019, Samsung Foundry announced the first v0.1 development kit of its new 3GAE process node using GAAFETs was being made available to key customers. At the time Samsung predicted volume production by end of 2021, and the latest announcement suggests that while 3GAE will deploy in 2022 internally, main customers may have to wait until 2023 for its more advanced 3GAP process.

To put this into a table:

Gate-All-Around Transistor Deployment
AnandTech Name Process Timeframe
Intel RibbonFET 20A 2024
18A 2025
TSMC GAAFET N2 / 2nm EoY 2023?
Samsung MBCFET 3GAE 2022
3GAP 2023

By this metric, Samsung might be first to the gate, albeit with an internal node, while TSMC is going to get a lot out of its N5, N4, and N3 nodes first. Around end of year 2023 is when it gets interesting as TSMC may be looking at its N2 designs, while Intel is committed to that 2024 timeframe. The official slide says first half 2024, though as a technology announcement vs product announcement, there is often some lag between the two.

 

New Technology Features for 2024: PowerVias

The other arm of Intel’s 20A designs in 2024 is what the company is calling ‘PowerVia’. The concept here pivots the traditional understanding of chip design from a multi-layered cake into a sandwich of sorts.

The manufacturing process of a modern circuit starts the transistor layer, M0, as the smallest layer. Above that, additional metal layers are added at increasing sizes to account for all the wiring needed between the transistors and different parts of the processor (cache, buffers, accelerators). A modern high-performance processor typically has anywhere from 10 to 20 metal layers in its design, with the top layer where the external connections are placed. The chip is then flipped over (known as flip chip) so that the chip can talk to the outside world with those connections on the bottom, and the transistors at the top.

With PowerVias, we now put the transistors in the middle of the design. On one side of the transistors we put the communication wires that allow parts of the chip to talk to each other. On the other side are all the power related connections (along with power gating control). In essence, we moved to a sandwich where the transistors are the filling. This is usually referred to as ‘backside power delivery’ in the industry – PowerVia is Intel’s marketing name.

From a holistic level, we can ascertain that the benefits of this design start with simplifying both the power and the connectivity wires. Typically these have to be designed to ensure there is no signaling interference, and one of the big sources of interference are large power carrying wires, so this takes them out of the equation by putting them on the other side of the chip. It also works the other way – the interference of the interconnected data wires can increase the power delivery resistance, resulting in lost energy and thermals. In this way, PowerVias can help new generations of transistors as drive currents increase by having the power directly there, rather than routed around the connectivity.

There are a couple of hurdles here to mention however. Normally we start manufacturing the transistors first because they are the most difficult and most likely to have defects – if a defect is caught early in the metrology (defect detection in manufacturing), then that can be reported as early in the cycle as possible. By having the transistors in the middle, Intel would now be manufacturing several layers of power first before getting to the tough bit. Now technically these layers of power would be super easy compared to the transistors, and nothing is likely to go wrong, but it is something to consider.

The second hurdle to think about is power management and thermal conductivity. Modern chips are built transistor first into a dozen layers ending with power and connections, and then the chip is flipped, so the power hungry transistors are now at the top of the chip and the thermals can be managed. In a sandwich design, that thermal energy is going to go through whatever ends up on the top of the chip, which is most likely going to be the internal communication wires. Assuming that the thermal increase of these wires doesn’t cause any issues in production or regular use, then perhaps this isn’t so much of an issue, however it is something to consider when heat has to be conducted away from the transistors.

It is worth noting that this ‘backside power delivery’ technology has been in development for a number of years. Across five research papers presented at the VLSI symposium in 2021, imec presented several papers on the technology showing recent advancements when using FinFETs, and in 2019 Arm and imec announced similar technology on an Arm Cortex-A53 built on an equivalent 3nm process in imec’s research facilities. Overall the technology reduces the IR drop on the design, which is becoming increasingly harder to achieve on more advanced process node technologies to drive performance. It will be interesting to see the technology when it is in high volume on high performance processors.

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  • bigboxes - Tuesday, July 27, 2021 - link

    Yeah, Intel is still king of the liars. I've got a box full of Intel CPUs, but Intel really crapped the bed. Intel 7 is the new 10nm. Can't make this stuff up! We can't put out a competitive product so we'll call it 7 anyways! GO INTEL GO!
  • Geef - Saturday, July 31, 2021 - link

    At least Intel is consistent. They have consistently added a + to their 14nm chips every single year!
  • mode_13h - Sunday, August 1, 2021 - link

    :D
  • aovander - Tuesday, August 3, 2021 - link

    Which is exactly what TSMC did with their 14nm node.
    This was how the whole naming problem got started but no one seemed to care since it seemed like they were catching up to Intel and all the Intel haters were happy to see it.

    When Intel shocked the world and released its FinFET (Tri-Gate) process at 22nm TSMC followed it with the horrible 20nm planar node though it had lower transistor density than Intel 22nm. TSMC was claiming its 20nm node was a half shrink of the 22nm node and therefore meant they were keeping up with Intel. TSMC felt they were justified in this because Intel 22nm transistor density missed the target of a full node shrink by a bit with the introduction FinFET's. This was a consequence of the new trench contact structure required between the Fin’s and Metal 0. TSMC has the same problem when they introduce Fin’s. Then, Intel released 2nd Gen FinFET, the 14nm node, with more than a full node of shrinkage to get back on track with what they missed at 22nm.

    TSMC then released their 14nm node shortly after with the same backend as the 20nm node - so no transistor density scaling, it was the same node really (sound familiar). Then, Intel got over-optimistic and tried to scale more than a full node again using Spacer Quad patterning at 10nm and got stuck in a 6 year delay. At the same time they decided to pass on using EUV for 10nm because at the time it was not ready for production.

    TSMC bought up all the EUV steppers in the world and then proceeded down the lithographic scaling trail of 10nm, 7nm, 5nm, and soon 3nm. A smart move on their part and easier to make since the throughput of the EUV tool increased in the meantime (since they were a bit behind Intel in that development decision). Essentially all this scaling was handed to them on a silver platter by ASML. Also, the transistor density of these 3-4 nodes has been well off the traditional density shrink which is why Intel 2 nodes (or more depending on how you interpret the marketing names) still has a density that matches them.

    They did not produce any real innovations in any of those nodes. Gate-all-around has been the obvious next step for 5-6 years. If they were "innovating" all this time with all these new nodes why did they not develop this. Now we see everyone claiming to have it ready to go in the 2024-2025 timeframe since IBM made their 2nm announcement. Funny how that is, wonder where everyone is getting it from?

    All I am saying is, if you are going to call Intel a Liar then you have to call everyone else one first.

    Given the confusion in the industry and the desire to truly compare technologies names with matched Transistor density, the whole world pushed Intel into changing their naming scheme since there was no possibility of getting the foundries to go backwards.
  • mode_13h - Wednesday, August 4, 2021 - link

    @aovander thanks for the info.

    As I've said several times, Intel can just name their node with a monotonically increasing sequence that has no obvious or direct relation to density. Just opt out of the whole nm race, entirely.
  • Dex4Sure - Tuesday, November 23, 2021 - link

    Intel's 10nm is actually slightly better than TSMC's 7nm in density... So they may as well call it "Intel 7".
  • Butterfish - Tuesday, July 27, 2021 - link

    Any proof? Or just pulling thin air out of your arse to satisfy your agenda? The density comparison graph in the first page of this article literally disapprove your statement.
  • Spunjji - Wednesday, July 28, 2021 - link

    @Butterfish - not to agree with DigitalFreak here, but it's worth noting that Intel haven't actually managed to produce a shipping design anywhere near their quoted density for 10nm, while TSMC customers (most notably AMD) have come much closer to their quoted density.

    I'd still say that 10ESF looks broadly comparable to TSMC 7nm, though - much moreso than Samsung's 8nm.
  • Butterfish - Thursday, July 29, 2021 - link

    Yes they have. The Cannon Lake Core i3-8121U did use the high density libraries that has the advertised maximum density for 10nm.
  • Spunjji - Friday, July 30, 2021 - link

    @Butterfish - You're citing the broken chip that only shipped in one cut-price notebook; one that doesn't have public figures for transistor count available, so we don't know anything for sure about the density. The possibilities are either that you're technically correct in the worst way - i.e. they haven't shipped anything that /worked properly/ with their quoted 100M density - or you're wrong on both counts. 🤷‍♂️

    Back in the world of numbers we know for sure, Lakefield hit almost exactly 49% of their quoted 10nm density, and that had all the inconvenient I/O stuff shunted off to its secondary die.

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