One of the main features Intel was promoting at the launch of Haswell was TSX – Transactional Synchronization eXtensions. In our analysis, Johan explains that TSX enables the CPU to process a series of traditionally locked instructions on a dataset in a multithreaded environment without locks, allowing each core to potentially violate each other’s shared data. If the series of instructions is computed without this violation, the code passes through at a quicker rate – if an invalid overwrite happens, the code is aborted and takes the locked route instead. All a developer has to do is link in a TSX library and mark the start and end parts of the code.

News coming from Intel’s briefings in Portland last week boil down to an erratum found with the TSX instructions. Tech Report and David Kanter of Real World Technologies are stating that a software developer outside of Intel discovered the erratum through testing, and subsequently Intel has confirmed its existence. While errata are not new (Intel’s E3-1200 v3 Xeon CPUs already have 140 of them), what is interesting is Intel’s response: to push through new microcode to disable TSX entirely. Normally a microcode update would suggest a workaround, but it would seem that this a fundamental silicon issue that cannot be designed around, or intercepted at an OS or firmware/BIOS level.

Intel has had numerous issues similar to this in the past, such as the FDIV bug, the f00f bug and more recently, the P67 B2 SATA issues. In each case, the bug was resolved by a new silicon stepping, with certain issues (like FDIV) requiring a recall, similar to recent issues in the car industry. This time there are no recalls, the feature just gets disabled via a microcode update.

The main focus of TSX is in server applications rather than consumer systems. It was introduced primarily to aid database management and other tools more akin to a server environment, which is reflected in the fact that enthusiast-level consumer CPUs have it disabled (except Devil’s Canyon). Now it will come across as disabled for everyone, including the workstation and server platforms. Intel is indicating that programmers who are working on TSX enabled code can still develop in the environment as they are committed to the technology in the long run.

Overall, this issue affects all of the Haswell processors currently in the market, the upcoming Haswell-E processors and the early Broadwell-Y processors under the Core M branding, which are currently in production. This issue has been found too late in the day to be introduced to these platforms, although we might imagine that the next stepping all around will have a suitable fix. Intel states that its internal designs have already addressed the issue.

Intel is recommending that Xeon users that require TSX enabled code to improve performance should wait until the release of Haswell-EX. This tells us two things about the state of Haswell: for most of the upcoming LGA2011-3 Haswell CPUs, the launch stepping might be the last, and the Haswell-EX CPUs are still being worked on. That being said, if the Haswell-E/EP stepping at launch is not the last one, Intel might not promote the fact – having the fix for TSX could be a selling point for Broadwell-E/EP down the line.

For those that absolutely need TSX, it is being said that TSX can be re-enabled through the BIOS/firmware menu should the motherboard manufacturer decide to expose it to the user. Reading though Intel’s official errata document, we can confirm this:

We are currently asking Intel what the required set of circumstances are to recreate the issue, but the erratum states ‘a complex set of internal timing conditions and system events … may result in unpredictable system behaviour’. There is no word if this means an unrecoverable system state or memory issue, but any issue would not be in the interests of the buyers of Intel’s CPUs who might need it: banks, server farms, governments and scientific institutions.

At the current time there is no road map for when the fix will be in place, and no public date for the Haswell-EX CPU launch.  It might not make sense for Intel to re-release the desktop Haswell-E/EP CPUs, and in order to distinguish them it might be better to give them all new CPU names.  However the issue should certainly be fixed with Haswell-EX and desktop Broadwell onwards, given that Intel confirms they have addressed the issue internally.

Source: Twitter, Tech Report


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  • otherwise - Wednesday, August 13, 2014 - link

    Before Devil's Canyon only Xeon's had TSX enabled and this was clearly laid out by Intel. I don't know what you were expecting.
  • TiGr1982 - Wednesday, August 13, 2014 - link

    No, that's not the case. Devil's Canyon i7 and i5 are the first UNLOCKED SKUs to feature TSX.

    Besides Devil's Canyon, a lot of other locked Core i7 and i5 support TSX right from Haswell introduction in June 2013 (more than a year ago) e.g. Core i7-4770 (without K) and so on.
  • TiGr1982 - Tuesday, August 12, 2014 - link

    This is reminiscent of the infamous Pentium FDIV bug in a sense that it was made available to the public by a non-Intel person much later than the relevant products were released to the market.
    20 years have passed since FDIV bug, but Intel still drops the ball from time to time - they still can't do their testing right and in advance...
  • coburn_c - Tuesday, August 12, 2014 - link

    Their release schedule is very aggressive and they put a lot of Investor relations into it. I wouldn't rule out that they would overlook such things to stick to it.
  • TiGr1982 - Tuesday, August 12, 2014 - link

    Yes, but this does not excuse them much.
  • nicmonson - Tuesday, August 12, 2014 - link

    Yes it does. Every chip company takes risks because there is only so much validation you can make before your competitor beats you to the punch. It even mentions in the article that there have been a bunch of them and their competitors have a bunch too.
  • madmilk - Wednesday, August 13, 2014 - link

    It is for precisely this reason that the -E/EP CPUs are one generation behind and -EX CPUs are two generations behind the latest and greatest. More time for validation.
  • Assimilator87 - Wednesday, August 13, 2014 - link

    Funny you should say that. Remember the VT-d errata in the C1 stepping of Sandy Bridge-E/EP?
  • psyq321 - Wednesday, August 13, 2014 - link

    Fortunately for Intel, most SNB-EP Xeons ended up being C2 stepping, since the bug was discovered while SNB-EP was still in C0/C1 qualification stage (SNB-E was not that lucky, since they were launched several months earlier).

    This time, it does not seem that the staggered launch saved EP. EX, on the other hand, yes.

    But in any case, the strategy Intel is employing is smart. There is a year between the first consumer and first EP SKUs, and two years between consumer and EX parts. During that time they do manage to kill lots of issues, which is especially important for EX line which is tailored for mission-critical operations.
  • lmcd - Wednesday, August 13, 2014 - link

    Hilariously enough, that was actually fixed in BIOS for SNB-E -- I have a C1 stepping SNB-E with enabled VT-d. So now that you mention it, this probably will get fixed for most affected parties.

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