Currently the majority of high-end processors are monolithic, but design methodologies are slowly but surely shifting to multi-chiplet modules as leading-edge fabrication technologies get more expensive to use. In the coming years multi-chiplet system-in-packages (SiPs) are expected to become much more widespread, and advanced 2.5D and 3D chip packaging technologies will gain importance. To accelerate and simplify development of 3D designs, TSMC this week established its 3DFabric Alliance. While multi-chiplet SiPs promise to simplify development and verification of highly complex designs, they require brand-new development methodologies as 3D packages bring a number of new challenges. This includes new design flows required for 3D integration, new methods of power delivery, new packaging technologies, and new testing techniques. To make the best use of the benefits of...

As HPC Chip Sizes Grow, So Does the Need For 1kW+ Chip Cooling

One trend in the high performance computing (HPC) space that is becoming increasingly clear is that power consumption per chip and per rack unit is not going to stop...

40 by Anton Shilov on 6/27/2022

3DFabric: The Home for TSMC’s 2.5D and 3D Stacking Roadmap

Interposers. EMIB. Foveros. Die-to-die stacking. ODI. AIB.TSVs. All these words and acronyms have one overriding feature – they are all involved in how two bits of silicon physically connect...

9 by Dr. Ian Cutress on 9/2/2020

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