AMD on Tuesday formally announced its next-generation EPYC processor code-named Rome. The new server CPU will feature up to 64 cores featuring the Zen 2 microarchitecture, thus providing at least two times higher performance per socket than existing EPYC chips.

As discussed in a separate story covering AMD’s new ‘chiplet’ design approach, AMD EPYC ‘Rome’ processor will carry multiple CPU chiplets manufactured using TSMC’s 7 nm fabrication process as well as an I/O die produced at a 14 nm node. As it appears, high-performance ‘Rome’ processors will use eight CPU chiplets offering 64 x86 cores in total, as well as an eight-channel DDR4 memory controller supporting up to 4 TB of DRAM per socket. Besides, the new processor supports 128 PCIe 4.0 lanes to connect next-generation accelerators, such as the Radeon Instinct MI60 based on the Vega 7nm GPU.

Considering the fact that Zen 2 microarchitecture is expected to generally increase performance of CPU cores (especially when it comes to floating point performance, which AMD expects to double), the Rome processors will boost performance of servers quite dramatically when compared to existing machines. In particular, AMD expects performance per socket to double as a result of higher core count, and predicts that floating point performance per socket will quadruple because of arhitectural IPC improvements and increase of the core count.

One important peculiarity of AMD’s EPYC ‘Rome’ processor is that it is socket compatible with existing EPYC ‘Naples’ platform and will be forward compatible with AMD’s future ‘Milan’ platforms featuring CPUs powered by the Zen 3 microarchitecture. This will greatly simplify development of AMD-based servers and will enable server makers to reuse their existing designs for future machines, which is important for AMD that needs to capture market from Intel. To do that, it has to simplify job of server builders by making its platforms simple.

AMD is currently sampling its EPYC ‘Rome’ processor with server makers and customers. The company plans to launch ‘Rome’ products sometimes in 2019, but it does not disclose its launch schedule just now.

This is a breaking news. We are updating the news story with more details.

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  • SaturnusDK - Wednesday, November 7, 2018 - link

    What chipset? EPYC never had a chipset, nor will EPYC2.
  • twtech - Tuesday, November 6, 2018 - link

    I wonder what clockrate this will run at with all cores loaded. And if they'll have a high-clockspeed 32-core variant designed for workstation use.
  • stephenbrooks - Tuesday, November 6, 2018 - link

    Photo #2 makes it looks like the I/O chip is made by Apple... and who's that being reflected in photo #1?
  • CheapSushi - Tuesday, November 6, 2018 - link

    This looks awesome. I'm digging the IBM style package. They took a bit chance on this approach and it's working out well.
  • Ej24 - Tuesday, November 6, 2018 - link

    128 pcie 4.0 lanes. Holy crap. That's insane. That's 256GB/s of i/o. That's huge. Is there a bottleneck on that? As in, if you populated an epyc system with ~60 theoretical pcie 4.0 x2 nvme drives and tried to access the simultaneously would you have full throughput?
  • SaturnusDK - Wednesday, November 7, 2018 - link

    The die shot confirms the old saying: "Rome wasn't built on one die".
  • jospoortvliet - Wednesday, November 7, 2018 - link

    Might very well be the background of the name...
  • Zizy - Wednesday, November 7, 2018 - link

    I find something strange in the slide deck - 4TB max for the single socket??? Huhm? How does that work, did AMD find higher capacity sticks or what?
  • Ryan Smith - Wednesday, November 7, 2018 - link

    Yes. 16Gbit DRAM chips are now in the pipeline.
  • Rοb - Wednesday, November 7, 2018 - link

    So if I want a 16-24 core ‘Rome’ processor it will be low cost, due to 5 or 6 dead cores on each chiplet ... ?

    It might be an idea to produce a 2 and 4 chiplet version, with 8 to 6 working cores - workstation laptop.

    I'd rather have 32 cores at double the clocks, running under 200W - more useful than 64 cores at half the speed (not in _every_ case, I know!).

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