It’s no secret that Intel’s enterprise processor platform has been stretched in recent generations. Compared to the competition, Intel is chasing its multi-die strategy while relying on a manufacturing platform that hasn’t offered the best in the market. That being said, Intel is quoting more shipments of its latest Xeon products in December than AMD shipped in all of 2021, and the company is launching the next generation Sapphire Rapids Xeon Scalable platform later in 2022. Beyond Sapphire Rapids has been somewhat under the hood, with minor leaks here and there, but today Intel is lifting the lid on that roadmap.

State of Play Today

Currently in the market is Intel’s Ice Lake 3rd Generation Xeon Scalable platform, built on Intel’s 10nm process node with up to 40 Sunny Cove cores. The die is large, around 660 mm2, and in our benchmarks we saw a sizeable generational uplift in performance compared to the 2nd Generation Xeon offering. The response to Ice Lake Xeon has been mixed, given the competition in the market, but Intel has forged ahead by leveraging a more complete platform coupled with FPGAs, memory, storage, networking, and its unique accelerator offerings. Datacenter revenues, depending on the quarter you look at, are either up or down based on how customers are digesting their current processor inventories (as stated by CEO Pat Gelsinger).

That being said, Intel has put a large amount of effort into discussing its 4th Generation Xeon Scalable platform, Sapphire Rapids. For example, we already know that it will be using >1600 mm2 of silicon for the highest core count solutions, with four tiles connected with Intel’s embedded bridge technology. The chip will have eight 64-bit memory channels of DDR5, support for PCIe 5.0, as well as most of the CXL 1.1 specification. New matrix extensions also come into play, along with data streaming accelerators, quick assist technology, all built on the latest P-core designs currently present in the Alder Lake desktop platform, albeit optimized for datacenter use (which typically means AVX512 support and bigger caches). We already know that versions of Sapphire Rapids will be available with HBM memory, and the first customer for those chips will be the Aurora supercomputer at Argonne National Labs, coupled with the new Ponte Vecchio high-performance compute accelerator.

The launch of Sapphire Rapids is significantly later than originally envisioned several years ago, but we expect to see the hardware widely available during 2022, built on Intel 7 process node technology.

Next Generation Xeon Scalable

Looking beyond Sapphire Rapids, Intel is finally putting materials into the public to showcase what is coming up on the roadmap. After Sapphire Rapids, we will have a platform compatible Emerald Rapids Xeon Scalable product, also built on Intel 7, in 2023. Given the naming conventions, Emerald Rapids is likely to be the 5th Generation.

Emerald Rapids (EMR), as with some other platform updates, is expected to capture the low hanging fruit from the Sapphire Rapids design to improve performance, as well as updates from the manufacturing. With platform compatibility, it means Emerald will have the same support when it comes to PCIe lanes, CPU-to-CPU connectivity, DRAM, CXL, and other IO features. We’re likely to see updated accelerators too. Exactly what the silicon will look like however is still an unknown. As we’re still new in Intel’s tiled product portfolio, there’s a good chance it will be similar to Sapphire Rapids, but it could equally be something new, such as what Intel has planned for the generation after.

After Emerald Rapids is where Intel’s roadmap takes on a new highway. We’re going to see a diversification in Intel’s strategy on a number of levels.

Starting at the top is Granite Rapids (GNR), built entirely of Intel’s performance cores, on an Intel 3 process node for launch in 2024. Previously Granite Rapids had been on roadmaps as an Intel 4 node product, however, Intel has stated to us that the progression of the technology as well as the timeline of where it will come into play makes it better to put Granite on that Intel 3 node. Intel 3 is meant to be Intel’s second-generation EUV node after Intel 4, and we expect the design rules to be very similar between the two, so it’s not that much of a jump from one to the other we suspect.

Granite Rapids will be a tiled architecture, just as before, but it will also feature a bifurcated strategy in its tiles: it will have separate IO tiles and separate core tiles, rather than a unified design like Sapphire Rapids. Intel hasn’t disclosed how they will be connected, but the idea here is that the IO tile(s) can contain all the memory channels, PCIe lanes, and other functionality while the core tiles can be focused purely on performance. Yes, it sounds like what Intel’s competition is doing today, but ultimately it’s the right thing to do.

Granite Rapids will share a platform with Intel’s new product line, which starts with Sierra Forest (SRF) which is also on Intel 3. This new product line will be built from datacenter optimized E-cores, which we’re familiar with from Intel’s current Alder Lake consumer portfolio. The E-cores in Sierra Forest will be a future generation than the Gracemont E-cores we have today, but the idea here is to provide a product that focuses more on core density rather than outright core performance. This allows them to run at lower voltages and parallelize, assuming the memory bandwidth and interconnect can keep up.

Sierra Forest will be using the same IO die as Granite Rapids. The two will share a platform – we assume in this instance this means they will be socket compatible – so we expect to see the same DDR and PCIe configurations for both. If Intel’s numbering scheme continues, GNR and SRF will be Xeon Scalable 6th Generation products. Intel stated to us in our briefing that the product portfolio currently offered by Ice Lake Xeon products will be covered and extended by a mix of GNR and SRF Xeons based on customer requirements. Both GNR and SRF are expected to have full global availability when launched.

The E-core Sierra Forest focused on core density will end up being compared to AMD’s equivalent, which for Zen4c will be called Bergamo – AMD might have a Zen5 equivalent when SRF comes to market.

I asked Intel whether the move to GNR+SRF on one unified platform means the generation after will be a unique platform, or whether it will retain the two-generation retention that customers like. I was told that it would be ideal to maintain platform compatibility across the generations, although as these are planned out, it depends on timing and where new technologies need to be integrated. The earliest industry estimates (beyond CPU) for PCIe 6.0 are in the 2026 timeframe, and DDR6 is more like 2029, so unless there are more memory channels to add it’s likely we’re going to see parity between 6th and 7th Gen Xeon.

My other question to Intel was about Hybrid CPU designs – if Intel was now going to make P-core tiles and E-core tiles, what’s stopping a combined product with both? Intel stated that their customers prefer uni-core designs in this market as the needs from customer to customer differ. If one customer prefers an 80/20 split on P-cores to E-cores, there’s another customer that prefers a 20/80 split. Having a wide array of products for each different ratio doesn’t make sense, and customers already investigating this are finding out that the software works better with a homogeneous arrangement, instead split at the system level, rather than the socket level. So we’re not likely to see hybrid Xeons any time soon. (Ian: Which is a good thing.)

I did ask about the unified IO die - giving the same P-core only and E-core only Xeons the same number of memory channels and I/O lanes might not be optimal for either scenario. Intel didn’t really have a good answer here, aside from the fact that building them both into the same platform helped customers synergize non-returnable development costs across both CPUs, regardless of the one they used. I didn’t ask at the time, but we could see the door open to more Xeon-D-like scenarios with different IO configurations for smaller deployments, but we’re talking products that are 2-3+ years away at this point.

Xeon Scalable Generations
Date AnandTech Codename Abbr. Max
Cores
Node Socket
Q3 2017 1st Skylake SKL 28 14nm LGA 3647
Q2 2019 2nd Cascade Lake CXL 28 14nm LGA 3647
Q2 2020 3rd Cooper Lake CPL 28 14nm LGA 4189
Q2 2021 Ice Lake ICL 40 10nm LGA 4189
2022 4th Sapphire Rapids SPR * Intel 7 LGA 4677
2023 5th Emerald Rapids EMR ? Intel 7 **
2024 6th Granite Rapids GNR ? Intel 3 ?
Sierra Forest SRF ? Intel 3
>2024 7th Next-Gen P ? ? ? ?
Next-Gen E
* Estimate is 56 cores
** Estimate is LGA4677

For both Granite Rapids and Sierra Forest, Intel is already working with key ‘definition customers’ for microarchitecture and platform development, testing, and deployment. More details to come, especially as we move through Sapphire and Emerald Rapids during this year and next.

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  • kpb321 - Thursday, February 17, 2022 - link

    I'm kinda surprised the E core only Xeon is so far out. After seeing the performance of 4 E cores in roughly the same die space as one P core for the consumer chips on multithreaded stuff it seemed like such an obvious move. I'd expect the E cores to do even better in servers as they can't run the P cores as high up the power/performance curve in the server chips so they'll loose some of their clock speed advantage. Reply
  • Calin - Friday, February 18, 2022 - link

    On the other hand, more cores usually put more pressure on the memory subsystem. Maybe using 4x the E-cores instead of the P-cores is too much.
    Remember that, when tasks takes twice as long to complete you have twice as many tasks "in flight" and you need twice the memory.
    So, a "machine gun" approach of nibbling on many tasks is less efficient (in average time for execution and average memory use) than a few big cores.
    As always, your mileage may vary.
    Reply
  • Mike Bruzzone - Friday, February 18, 2022 - link

    mb Reply
  • Hifihedgehog - Monday, February 21, 2022 - link

    Please ban Mike Bruzzone. He just keeps replying mb to everyone. Do we really need to see your initials everywhere, Mike? Reply
  • Mike Bruzzone - Monday, February 21, 2022 - link

    Hifhedgehog - Hi Hedgehog, when I read someone's observation and find it important, first to me as an analyst, and second to my Federal Trade Commission audit enlisted by federal attorneys retained by Congress of the United States, by my initials, my intent is to notify the author I found value in their observation and that I read it.

    You observe I also respond, raise inquires, collaboratively contribute, constructively confront as we are here, more or less, I don't support boycott, and give credit where I see credit due. I admit I initialed one comment twice was a typo. I can't respond to all observations I find valuable, but I can acknowledge when I find value I recognize the contribution.

    Thanks for your observation. mb
    Reply
  • mode_13h - Tuesday, February 22, 2022 - link

    > to my Federal Trade Commission audit

    This is interesting. If there's any public information about this audit, feel free to give us a link. Entirely up to you, but it would be education for some here.

    I think it's valuable for the public to gain a greater understanding of the role played by the federal government in industry and the economy. Most people don't understand how instrumental it is to the markets and industries that we all take for granted.

    > I also respond, raise inquires, collaboratively contribute, constructively confront

    I find your posts informative and informed, even if they're often so deep and outside my domain that I often just skim them. Thanks for contributing.
    Reply
  • Mike Bruzzone - Tuesday, February 22, 2022 - link

    Mode_13

    Thank you and appreciate what I observe as your sense of enterprise across and incorporating practice areas.

    My general comment string is here I rely on Seeking Alpha;

    https://seekingalpha.com/user/5030701/comments

    My analysis is here also at Seeking Alpha who has changed blog spot availability and I'll address that in the future on how I post primarily, slide sets;

    https://seekingalpha.com/user/5030701/instablogs

    I comment from time to time and simultaneously post data on The Next Platform simply search Mike Bruzzone and Next Platform.

    I also comment on Semi Wiki.

    Exhibits validating my FTC and USDOJ credential can be found on Pacer associated with this Federal Court of Claims case matter: 1:21-cv-01261-RTH. Otherwise, I'm engaged in numerous litigations with Intel pursuant Intel Inside price fix recovery and other issues associated with tech gang land are searchable my counsel is patience and persistence in the face of Intel associate network falsities.

    Pursuant Intel I can vouch for monopoly remedial advances beginning at Krzanich and continuing under Gelsinger but far from complete pursuant Intel legal department and legal network, on Intel generally recovering from monopolization, sabotage and robbery, both consumer associated with Intel Inside price fix and from the Entity itself on employee's engaged in cartel product laundering thefts primarily from DCG.

    Mike Bruzzone, Camp Marketing
    Reply
  • GeoffreyA - Wednesday, February 23, 2022 - link

    I also appreciate your contributions, Mike, even though they're largely out of my grasp of understanding. Reply
  • Mike Bruzzone - Thursday, February 24, 2022 - link

    GeoffreyA, you're welcome I'm open to inquiry, observation, adds, point - counter point anytime. mb Reply
  • Kamen Rider Blade - Thursday, February 17, 2022 - link

    Now, for Intel to bring PURE P-core & E-core CPU's to the Desktop product stack and STOP being stingy on the core counts.

    Leave Hybridization for the Mobile market.
    Reply

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