As part of the second leg of TSMC's spring technology symposium series, the company offered an update on the state of its 3nm-class processes, both current and future. Building on the back of their current-generation N3E process, the optical shrink of this process technology, N3P, is now on track to enter mass production in the second half of 2024. Thanks to that shrink, N3P is expected to offer both increased performance efficiency as well as increased transistor density over N3E.

N3E in Production, Yielding Well

With N3E already in volume production, TSMC is reporting that they're seeing "great" yields on the second-generation 3nm-class process note. According to the company, the D0 defect density of N3E is at relative parity with N5, matching the defect rate of the older node for the same point in its respective lifecycle. This is no small feat, given the additional complexities that come with developing one last, ever-finer generation of FinFET technology. So for TSMC's bleeding-edge customers such as Apple, who just launched their M4 SoC, this is allowing them to reap the benefits of the improved process node relatively quickly.

"N3E started volume production in the fourth quarter of last year, as planned," a TSMC executive said at the event. "We have seen great yield performance on customers' products, so they did go to market as planned."

TSMC's N3E node is a relaxed version of N3B, eliminating some EUV layers and completely avoiding the usage of EUV double patterning. This makes it a bit cheaper to produce, and in some cases it widens the process window and yields, though it comes at the cost of some transistor density.

N3P on Track For Second-Half 2024

Meanwhile, looking towards the immediate future at TSMC, N3P has finished qualification and its yield performance is close to N3E, according to the company. Being an optical shrink, the N3P node is set to enable processor developers to either increase performance by 4% at the same leakage or reduce power consumption by 9% at the same clocks (previously the range was between 4% ~ 10% depending on design). The new node is also set to boost transistor density by 4% for a 'mixed' chip design, which TSMC defines as a processor consisting of 50% logic, 30% SRAM, and 20% analog circuits.

Advertised PPA Improvements of New Process Technologies
Data announced during conference calls, events, press briefings and press releases
Power -25-30% -32% -5% ~ 10% higher
Performance +10-15% +18% +5% +5%
Fmax @ 1.2V
Chip Density ? ? 1.04x same
SRAM Cell Size 0.0199µm² (-5% vs N5) 0.021µm² (same as N5) ? ?
Late 2022 H2 2023 H2 2024 2025

While it looks like the original N3 (aka N3B) will have a relatively muted lifecycle since Apple has been its only major customer, N3E will be adopted by a wide range of TSMC's customers, which includes many of the industry's biggest chip designers. 

Since N3P is an optical shrink of N3E, it is compatible with its predecessor in terms of IP blocks, process rules, electronic design automation (EDA) tools, and design methodology. As a result, TSMC expects the majority of new tape outs to use N3P, not N3E or N3. This is logical as N3P provides higher performance efficiency than N3E at a lower cost than N3.

The most important aspect of N3P is that it is on track to be production ready in the second half of this year, so expect chip designers to adopt it straight away. 

"We have also successfully delivered N3P technology," the TSMC executive said. "It has passed qualification and yield performance is close to N3E. [The process technology] has also received product customer tape outs and will start on production in the second half of this year. Because of [PPA advantages] of N3P, we expect the majority of tape outs on N3 to go to N3P."

Source: European Technology Symposium 2024



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  • OreoCookie - Saturday, May 18, 2024 - link

    If true, that does not bode well for Rapidus and their, hmmm, ambitious timeline. Reply
  • name99 - Thursday, May 16, 2024 - link

    Look at how TSMC has ALWAYS done things. They progress slowly, one big step at a time.
    Coming up, the big steps that matter are
    - GAA
    - BSPD
    - THEN finer lithography via high-HA EUV.

    They don't need to get those high-NA EUV machines right now.

    Intel is trying to short-circuit the process but look at the details.
    They claim GAA and BSPD together in 20A, (this year!) followed by 18A (also this year!)
    Will that happen? Supposedly Arrow Lake will be released before the end of the year on 20A. But already rumors are that most Arrow Lake compute tiles will not be on 20A. so ???

    Will Lunar Lake ship in 2025 on 18A? Well, lets start by seeing what happens with Arrow Lake.

    Meanwhile even the optimistic Intel roadmaps only put high-NA EUV as 14A at-risk in 2027.
    So TSMC is
    (probably) 2025 GAA, so maybe an Apple product SHIPPING in 2025
    (probably) 2026 BSPD in TSMC A16 node. Again maybe an Apple product w BSPD in 2026
    (maybe) 2028 TSMC A14 w/ high-NA EUV? Again maybe an Apple product w A14 in 2028

    These timelines are just not that different, especially if you go by "When can I buy the product in Best Buy?" (one week after Apple announcement, often one year after Intel announcement).
  • OreoCookie - Sunday, May 19, 2024 - link

    Yes, agreed, TSMC is taking a more cautious approach, introducing one key new tech per node if they can. Intel is pushing hard to make up lost ground. Then you have projects like Rapidus that have a low probability of success, but too much talent and funding to ignore and dismiss outright. IMHO it is an exciting time to be in the semiconductor industry.

    Regarding high-NA EUV, according to Semianalysis' cost model, it will be more expensive than if you used NA = 0.33 steppers instead. Some products like nVidia's compute dies (which almost fills the entire reticle) would either require stitching or a rethink of the architecture to allow for chiplets.
  • name99 - Thursday, May 16, 2024 - link
    (Chinese, but with subtitles) gives some numbers.

    He claims to see parts of the Apple A17 LOGIC that are 217 to 227 MTr/mm^2. This is about 65% over N5. That's also about what TSMC predicted which was around 1.7x

    He also has numbers for SRAM density, and various asides about parts of the die that are unused, providing the seal ring, scribe crack isolation, or voltage block isolation (which are all relevant if you want to generate a ballpark number by dividing number of transistors (usually known, since Apple usually tells us that) by chip "area" (the relevant area is rather less than the height*width you see when you decap the chip...)

    Of course SRAM has moved much less; we all knew this was coming before N3, we all know it after N3. That doesn't stop the usual idiots from making claims about how N3 buys you zero improved transistor density, TSMC lying, blah blah.

    The thing you have to look at whenever you see these claims is
    - are they talking about TRANSISTOR density or LOGIC density?
    - are they comparing to what TSMC said about TRANSISTOR density or about LOGIC density?
  • my_wing - Wednesday, May 15, 2024 - link

    Just a food for though from this article.

    TSMC N3B to N3E need a redesign.

    But those Fake News media i.e. MLID mentioned that Intel Lunar Lake is based on N3B, if Intel Lunar Lake / part of Lunar Lake is N3B then it is not an Apple specific node, although in my mind this is still a failed Node. Is your article and using some logics can conclude that MLID is fake new media, Intel Lunar Lake will not be based on TSMC N3 (Compute Tile)

    This is why I commented on the other post saying that "ha TSMC is slow but we are okay we gain Qualcomm as the customer"

    As you mentioned EDA compatible, because 2-3 years ago, Intel did mentioned that Qualcomm is special, they will co-develop using 20A, then if you look forward to now, Intel 20A is already is (if not already) pre-ramping. So if Qualcomm stuck with Intel, they already having a better node than its competitor i.e. TSMC N3E Vs Intel 20A. But Qualcomm do not want to invest, and please do not blame on Pat and Intel, they delivery but Qualcomm don't know what they sign up for, they don't want PSPD and GAA in 2024, they want FinEFT, they should have sign up for Intel 3.
  • Lodix - Thursday, May 16, 2024 - link

    Intel 20A is not for foundry business, it is just an internal node. It lacks a lot of IP and stuff. You can't make a whole mobile SoC using a half backed node. Reply
  • OreoCookie - Saturday, May 18, 2024 - link

    How do we know that 20A is a better node than N3E? And by what criteria? Intel's first 10 nm products showed clock speed regressions compared with 14++(+). A new transistor type does not necessarily mean better performance in its initial incarnation (vs. a highly-optimized FinFET design).

    I'd reserve judgement until we see products on the market, and we get yield numbers.
  • Terry_Craig - Thursday, May 16, 2024 - link

    From now on, designs will have to be more exotic. Caches still do not shrink with new nodes. AMD should continue applying its strategy with 6nm chiplets for caches.

    I wonder if adding Samsung to the equation would be viable at this point.
  • nandnandnand - Saturday, May 18, 2024 - link

    I'm not sure SRAM shrinks between N7 which it's on now and N6. But they could end up on N6 if N7 production winds down.

    What I want to see next is multiple layers. The 3D V-Cache chiplets are currently one single layer consisting of 64 MiB, but it's known they could stack additional layers. That comes at a greater cost, but it could become a good way to upsell to a flagship.
  • OreoCookie - Sunday, May 19, 2024 - link

    AFAIK scaling of memory cells is limited by scaling the capacitors. Simply put, they are very, very tall and have a very narrow base (they have a high aspect ratio). Increasing the aspect ratio (height-to-width) is difficult to impossible.

    That is why memory manufacturers have their own process nodes with their own naming conventions, which typically make no reference to some size.

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