AMD Clarifies Comments on 7nm / 7nm+ for Future Products: EUV Not Specifiedby Dr. Ian Cutress on March 5, 2020 6:50 PM EST
As part of AMD’s Financial Analyst Day 2020, the company gave the latest updates for its CPU and GPU roadmap. A lot of this we have seen before, with the company talking out to Zen 4 and Genoa on its datacenter CPU product line, out to Zen 3 and Ryzen 4000 with the consumer product line, and now with the RDNA/CDNA split between consumer and compute graphics. In previous graphs of a similar nature, AMD used the term ‘7nm+’ when referring to products beyond the first iteration of 7nm. AMD has today clarified to us that this does not mean they are using TSMC’s N7+ process node for those items.
TSMC has three high-level versions of its 7nm process:
- N7, which is the basic initial version using ‘DUV’ only tools (so no EUV),
- N7P, which is the second generation version of N7 which is also only DUV
- N7+, which is an EUV version of N7 for a number of layers in the metal stack
This nomenclature has been finalized within the past year or so.
Before this, AMD had presented various CPU and GPU roadmaps to the public. For the Zen 2 hardware, such as Ryzen 3000 series (Matisse), AMD had labeled this as ‘7nm’, which was all widely interpreted to mean TSMC’s N7 process. For future products, such as Zen 3, AMD had the slide listed as ‘7nm+’, which everyone had understood was ‘a better version of 7nm’.
From Next Horizons in July 2019
Because AMD labeled those as 7nm+, when TSMC called its version of 7nm with EUV to be N7+, one of the obvious assumptions that people have made is that where AMD wrote 7nm+, it was to be on the N7+ process. We have since learned that this is not entirely correct.
In order to avoid confusion, AMD is dropping the ‘+’ from its roadmaps. In speaking with AMD, the company confirmed that its next generations of 7nm products are likely to use process enhancements and the best high-performance libraries for the target market, however it is not explicity stating whether this would be N7P or N7+, just that it will be ‘better’ than the base N7 used in its first 7nm line.
This doesn’t necessarily mean that AMD isn’t going to be using EUV in the future – we were told it will be on a case by case basis, and at this time they wanted to clarify that AMD is not making any specific clarifications of which version of 7nm from TSMC it plans to use. More will be detailed at future events.
Interested in more of our AMD Financial Analyst Day 2020 Coverage? Click here.
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twotwotwo - Friday, March 6, 2020 - linkTSMC's N7+ seemed like an odd next step, because while N7 was design rule compatible with N7P and N6, N7+ apparently had different rules so it would require a different physical implementation (https://fuse.wikichip.org/news/2567/tsmc-talks-7nm... ). Whatever this is, maybe it lets them reuse parts of their previous gen's implementation.
On the other hand, this gen is supposed to be a new microarchitecture, so maybe it wouldn't have been *so* odd to implement it on a process with different design rules. We're all sorta wandering around in the dark trying to squeeze anything meaningful out of the little that's disclosed about the complicated mess of low-level design/manufacturing.
AnGe85 - Friday, March 6, 2020 - linkThere's nothing odd about it.
TSMC first developed the N7 (DUV and multipattering). Then, as an advancement, they implemented the (partial) use of EUV and developed the N7+ with 4 EUV layers (with first tapeouts in Oct.'18). Then they started to optimize the N7 to N7P, still DUV based. Both, N7+ and N7P were ready for mass production around mid 2019.
After that, they announced the N6 (five EUV layers), because they expect a lot of customers to stay on 7 nm processes for a longer period and they want to give them an easier opportunity to migrate from N7 or N7P (because the N7+ uses different design rules than the N7(P)).
lefty2 - Friday, March 6, 2020 - linkYep. N6 won't be in production until next year, which is why AMD can't use it for Milan or Navi 2X
jOHEI - Friday, March 6, 2020 - linkN7P came at the same time as N7+, but it was only announced as such later
CiccioB - Saturday, March 7, 2020 - linkN7P was probably plan B in case N7+ was not ready for mass production in time..
and it seem it is not
Fulljack - Monday, March 9, 2020 - linkI don't think TSMC has enough scale to produce N7+ chips at huge scale. Apple A13 and Qualcomm SD865 still use N7P manufacturing process, either because moving to N7+ prove too much of a hassle due to different design rules or TSMC couldn't mass production N7+ at Apple's or Qualcomm's scale.
Currently N7+ are only used by Kirin 990 5G (the one with integrated 5G modem).
scineram - Friday, March 6, 2020 - linkDidn't Shor say Navi is using N7P? This news does not help clarity.
Gondalf - Friday, March 6, 2020 - linkNobody want 7nm+ EUV this is a fact, TSMC have not big customers on it. Without good pellicles this process is a damnation.
Very likely we will see a plain 7nm version of Zen 3 with less enhancements in performance than expected. Better be able to supply the customers than to have a faster SKU with no good availability form foundries.
I remember that the real high volume pellicles for EUV will are available only at the beginning of 2021. This the reason Intel will be in volume on 7(5)nm EUV only at the end of 2021.
wolfesteinabhi - Friday, March 6, 2020 - linkN7+ is more of a "test"/"proof" vehicle for their EUV .. before going full dive into it with 5nm ..so they continur to use N7 and N7P with DUV and can offer N7+ in some limited capacity .. they will have alot learnings that would have helped them to develop N5 in a good way.
Korguz - Friday, March 6, 2020 - linkgondalf
" Nobody want 7nm+ EUV this is a fact " post proof of this " fact "
" Better be able to supply the customers than to have a faster SKU with no good availability form foundries. " like intel is doing with 14+++++++++++ and 10 nm ?
" This the reason Intel will be in volume on 7(5)nm EUV only at the end of 2021. " yea ok sure, again, can you prove this ??