I've read that switching speeds of 750 ps (that's picosecond, i.e. 0.75 ns!) have been achieved by researchers, though presumably by employing a 3 terminals and 2 transistors per cell, thus sacrificing half the density. Assuming a comparable process node with SRAM so that the features are roughly the same size, that is still 3 times the density of SRAM.
Even if it is impractical or makes no sense to use 3-terminal STT-MRAM for L1 cache, it could still be used for ultra fast L2 cache, while employing a standard (but faster than the current MRAM) 2-terminal - 1 transistor MRAM for L3 cache. I cannot easily assess the potential latency gain, but even if there was none due to the progressively increased size, CPUs could have 3 times the L2 cache and 6 times the L3 cache at the same size as having 1/3 the L2 and 1/6 the L3 SRAM cache!
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vortmax2 - Monday, August 6, 2018 - link
Very interesting. Samples already...let's see where this goes!Santoval - Monday, August 6, 2018 - link
I've read that switching speeds of 750 ps (that's picosecond, i.e. 0.75 ns!) have been achieved by researchers, though presumably by employing a 3 terminals and 2 transistors per cell, thus sacrificing half the density. Assuming a comparable process node with SRAM so that the features are roughly the same size, that is still 3 times the density of SRAM.Even if it is impractical or makes no sense to use 3-terminal STT-MRAM for L1 cache, it could still be used for ultra fast L2 cache, while employing a standard (but faster than the current MRAM) 2-terminal - 1 transistor MRAM for L3 cache. I cannot easily assess the potential latency gain, but even if there was none due to the progressively increased size, CPUs could have 3 times the L2 cache and 6 times the L3 cache at the same size as having 1/3 the L2 and 1/6 the L3 SRAM cache!
boozed - Wednesday, August 8, 2018 - link
The "MRAM revolution", like flying cars and cold fusion and hoverboards?